1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly to a high voltage generating device which generates high voltage by utilizing the charge pump technology.
2. Description of the Background Art
FIG. 11 shows a structure of a conventional high voltage generating device. As shown in FIG. 11, this high voltage generating device is connected to a load 9, and it includes a charge pump 1, an oscillator 3, a charge pump control circuit 5, and a detecting circuit 7.
Charge pump 1 generates a high voltage VPP in response to clock pulses .phi., /.phi. generated from oscillator 3. Specifically, when clock pulse /.phi. is at a high (H) level, for example, current flows from node N0 to N1, from node N2 to N3, and from node N4 to N5. A node N (2 m) has a higher potential than a node N(2 m+1) by approximately a threshold voltage.
When clock pulse /.phi. falls to a low (L) level, potentials of nodes N0 to N5 tend to decrease due to capacitance coupling. However, current supplied from the left side raises the potentials higher than they were when clock pulse /.phi. was previously at the L level. At this time, clock pulse .phi. attains the H level, and current is supplied from node N1 to N2 and from node N3 to N4.
When clock pulse .phi. returns to the L level, current is supplied again from node N0 to N1, from node N2 to N3, and from node N4 to N5, and nodes N1, N3, N5 have higher potentials than they did in the previous cycle. Assuming that current is supplied from left to right, and coupling ratio of capacitors C1, C2 and so on is .alpha., clock amplitude is Vosc, and a threshold voltage is V.sub.TN, then potential is raised by about (.alpha.Vosc-V.sub.TN) per stage.
Detecting circuit 7 detects an output voltage VPP of charge pump 1.
Specifically, output voltage VPP is divided by resistors R1 and R2, and a potential at a node between R1 and R2 is Vdev. Based on comparison between potential Vdev and a reference voltage Vref by comparator 71, detecting circuit 7 outputs an H level detecting signal Vdet if potential Vdev &gt;reference voltage Vref, and an L level detecting signal Vdet if potential Vdev &lt;reference voltage Vref.
Here, a desirable value of output voltage VPP from charge pump 1 is (R1+R2).multidot.Vref/R2.
Then, charge pump control circuit 5 stops oscillator 3 in response to the H level detecting signal from detecting circuit 7, and operates oscillator 3 in response to the L level detecting signal from detecting circuit 7.
A flash memory, for example, has a mode applying high voltage generated by a charge pump directly to memory cells. The number of memory cells receiving the high voltage varies in accordance with write or erase patterns. Therefore, magnitude of a load for a charge pump differs from one pattern to another. The performance of the charge pump should be determined so that it is sufficient for that one of the operation modes which has the maximum load.
Therefore, the load may become very light depending on the operation mode as described above. This results in overpower, making undesirable ripple phenomenon more conspicuous.